Demonstration: FPGA Based Network Monitoring Accelerator for 100Gb Ethernet

When
17/06/2015 11:30-12:00
Where
Demonstration area
CESNET and INVEA-TECH are prepared to demonstrate results of joint research project focused on 100GE network monitoring using FPGA. The demo will show functionality and unique features of FPGA design and hardware acceleration card with 100GE CFP2 LR4 interface (four 25Gb GTZ transceivers), Virtex-7 HT chip, QDR-IIIe memories and PCI gen3 x16 interface. Fast DMA engine and optimized Linux drivers were designed and implemented to achieve 100Gb data transfers through PCIe bus with low CPU utilization. Network traffic can be distributed among multiple CPU cores based on configurable hash functions. This means that the FPGA design provides wire-speed packet capture to the host memory and can utilize power of FPGA and CPU cores for various network monitoring applications.

The demo will show how packets can be received at 100Gbps speed and captured to the host memory. Processing speed will be demonstrated by counters and graphs showing generated, received and captured (by SW) packets. We will also show load of CPU cores during the packet capture for various packet lengths.